Photo of the day: APU AMD Renoir Crystal

The source posted an image that allegedly captured the first crystal of the AMD Renoir hybrid processor. This APU is designed for 7 nm release at TSMC capacities. A total of 9.8 billion transistors were formed on a 156 mm² chip. The picture clearly shows the CPU cores, a cluster of GPU computing units, built-in memory controllers, the south bridge and interfaces.
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The Renoir configuration includes eight CPU cores on the Zen 2 microarchitecture, which are grouped into two CCX complexes. Unlike similar blocks of Matisse and Rome multi-chip microcircuits, the Renoir CCX complex has only 4 MB of shared third-level cache memory. The source suggests that this is done due to the fairly low latencies of the memory controller. The amount of cache in the second level does not differ from what the processors have, and is 512 KB per core. In other words, the total cache is 12 MB.
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The graphics processor integrated into Renoir is a hybrid of Vega and Navi. More specifically, SIMD components are ported from Vega, while multimedia engines and a display controller are from Navi. The iGPU configuration includes eight NGCU clusters with 512 stream processors. The internal connection of the Infinity Fabric, which occupies a significant part of the chip, is used for communication between the components. The built-in memory controller is a two-channel one, supporting LPDDR4x (up to LPDDR4x-4233) and DDR4 (up to DDR4-3200) memory.

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